1. Field of the Invention
The present invention relates to a filter circuit for removing noise in a digital signal and, more specifically, for removing noise pulses of various widths from a digital input signal.
2. Description of the Related Art
For example as described in JP-2000-134070A, a noise reduction circuit removes noise from a series of digital signals by sampling signals input through a signal line. Because noise is mixed with a digital input signal as a pulse signal having a short width, the noise reduction circuit samples the input signal in accordance with a clock signal and removes any pulse signals having a width shorter than a predetermined width.
Specifically, the noise reduction circuit includes a plurality of delay devices for delaying the digital signal sequentially, a first logic circuit that generates a first determining signal when outputs of all the delay devices are at a logical high (H) level, a second logic circuit that generates a second determining signal when outputs of all the delay devices are at a logical low (L) level, and a reset-set (RS) flip-flop circuit that outputs a signal at the H level when the first determining signal is input and outputs a signal at the L level when the second determining signal is input.
The noise reduction circuit removes noise based only on a signal level at a sampling point. Thus, when noise signals each having a different level from an input signal and a width shorter than a sampling cycle are successively mixed with the input signal having a constant level at successive sampling points, the noise reduction circuit successively samples the different level over a predetermined number of times. As a result, the output of the RS flip-flop circuit is reversed and the noise signals are output as normal signals.